1. Field of the Invention
The present invention relates generally to an inter-LAN (local area network) communication system wherein a plurality of LANs are interconnected by an ATM switch, and more specifically to an address "learning" technique used at the interface between the ATM switch and the LANs.
2. Description of the Related Art
In a communication system in which local area networks such as Ethernet are interconnected by an ATM switch, the data handled by the LANs are in the form of variable bit rate (VBR) packets, while the data handled by the ATM switch are in the form of fixed length ATM cells whose payload contains source and destination addresses (SA, DA) and whose header contains a virtual path identifier (VPI) and a virtual channel identifier (VCI). A cell assembly disassembly unit is therefore provided at the interface between the ATM switch and each local area network to provide data format conversion between packets and ATM cells. ATM cells bearing the same address information are assembled into a packet, and an error check is performed on the packet using CRC (cyclic redundant check) bits before the packet is sent to a LAN. Prior art cell assembly disassembly (CLAD) units include an address table for storing the SA, VPI and VCI data of ATM-to-LAN cells whenever such a cell is received from the ATM switch. When a LAN-to-ATM packet is received, the CLAD unit searches the address table for an entry having the same destination address as that of the received packet. If such an entry is detected in the address table, the CLAD unit disassembles the packet into one or more payload segments depending on the packet length, and assembles ATM cells each with a header containing the VPI and VCI of the detected entry.
In addition, the address table is updated according to a "learning" process such that all entries of the table are first searched in response to receipt of an ATM cell to determine whether the same address data is already stored in any of the entries. If not, the cell address data is stored in a vacant entry. If the same address data is already stored in an entry, the registered data is replaced with the address data of the cell and the time-lapse indicator of the entry is reset to zero. The time-lapse indicator of each entry is incremented by a predetermined amount at periodic intervals. If the time-lapse indicator of an entry exceeds a predetermined threshold value, the address data of that entry is erased.
Since the CRC error check on the payload bits is performed after a packet is assembled, a provision is also made in the prior art CLAD unit to update the address table at the time when a CRC check reveals that there is no error in the payloads of the cells, so that corrupted source address data cannot be stored in the address table.
However, since the table is searched is performed each time an address-containing ATM cell is received and the time-lapse indicators of all stored table entries are incremented at periodic intervals, a heavy burden is placed on the cell assembly disassembly unit.